`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:31:42 05/25/2012 
// Design Name: 
// Module Name:    CODER2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CODER16(
/* input[15:0] BinaryData,//INPUT DATA
							//5 BITS OF BCD CODE
 output  reg[3:0]  coderConvData0=4'h0,
 output  reg[3:0]  coderConvData1=4'h0,
 output  reg[3:0]  coderConvData2=4'h0,
 output reg[3:0] coderConvData3=4'h0,
 output reg[3:0] coderConvData4=4'h0,
 
 input systemclock);*/
 		input wire systemclock,
		input wire reset,
		input wire chrCoderEn,
		input wire [16:0] chrCoderData,

		output reg coderConvEn,
		output reg [16:0] coderConvData,
		output reg CoderTestFlag
		);
		
		
wire [15:0] BinaryData = chrCoderData[15:0];

 wire[4:0] c_in;
 wire[4:0] c_out;
 reg [3:0] dec_sreg0=4'h0;
 reg [3:0] dec_sreg1=4'h0;
 reg [3:0] dec_sreg2=4'h0;
 reg [3:0] dec_sreg3=4'h0;
 reg [3:0] dec_sreg4=4'h0;
 
 
 wire[3:0] next_sreg0,next_sreg1,next_sreg2,next_sreg3,next_sreg4;
 
 
 
 reg [7:0] bit_cnt=8'h0;
 reg [15:0] bin_sreg;
 
 
 
 
wire load=~|bit_cnt;//LOAD THE BINARY DATA READY FOR TRANSFER
wire convert_ready= (bit_cnt==8'h11);//DONE
wire convert_end= (bit_cnt==8'h12);//DONE AND INTIALIZE NEXT LOOP

reg  outputFlag;


 
always @ (posedge systemclock)
begin
 if(load)bin_sreg<=BinaryData;
 else bin_sreg <={bin_sreg[14:0],1'b0};
end

assign c_in[0] =bin_sreg[15];
assign c_in[1] =(dec_sreg0>=5);
assign c_in[2] =(dec_sreg1>=5);
assign c_in[3] =(dec_sreg2>=5);
assign c_in[4] =(dec_sreg3>=5);


assign c_out[0]=c_in[1];
assign c_out[1]=c_in[2];
assign c_out[2]=c_in[3];
assign c_out[3]=c_in[4];
assign c_out[4]=(dec_sreg4>=5);

//CONFIRM THE OUTPUT
assign next_sreg0=c_out[0]? ({dec_sreg0[2:0],c_in[0]}+4'h6):({dec_sreg0[2:0],c_in[0]});
assign next_sreg1=c_out[1]? ({dec_sreg1[2:0],c_in[1]}+4'h6):({dec_sreg1[2:0],c_in[1]});
assign next_sreg2=c_out[2]? ({dec_sreg2[2:0],c_in[2]}+4'h6):({dec_sreg2[2:0],c_in[2]});
assign next_sreg3=c_out[3]? ({dec_sreg3[2:0],c_in[3]}+4'h6):({dec_sreg3[2:0],c_in[3]});
assign next_sreg4=c_out[4]? ({dec_sreg4[2:0],c_in[4]}+4'h6):({dec_sreg4[2:0],c_in[4]});

 

//LOAD THE DATA
always @ (posedge systemclock)
begin
 if(load) 
  begin 
   dec_sreg0<=4'h0;
   dec_sreg1<=4'h0;
   dec_sreg2<=4'h0;
   dec_sreg3<=4'h0;
   dec_sreg4<=4'h0;
  end   
 else  
  begin
   dec_sreg0<=next_sreg0;
   dec_sreg1<=next_sreg1;
   dec_sreg2<=next_sreg2;
   dec_sreg3<=next_sreg3;
   dec_sreg4<=next_sreg4;
  end
end

//OUTPUT
always @ (posedge systemclock)
if(reset)begin
		bit_cnt <= 4'h0;
		outputFlag <= 0;
		CoderTestFlag<=0;
end
else if(chrCoderEn)
		begin
		outputFlag <=1;
		bit_cnt <= 4'h0;
		CoderTestFlag<=1;
		end
else  begin
 if(convert_ready && outputFlag) 
  begin 
   coderConvData[3:0]<=dec_sreg0;
   coderConvData[7:4]<=dec_sreg1;
   coderConvData[11:8]<=dec_sreg2;
   coderConvData[15:12]<=dec_sreg3;
	coderConvData[16]<=chrCoderData[16];
	coderConvEn	<= 1;
	outputFlag  <= 0;
  end  
	if(convert_end) 
	begin
	bit_cnt<=4'h0;
	coderConvEn <=0;
	outputFlag<=0;
	end
	else bit_cnt<=bit_cnt+4'h1;   
end

endmodule
